We are seeking a Senior Design Engineer to work on complex protocol and subsystem architecture development for advanced IC products. The role involves RTL design, verification, and debugging of large-scale digital systems. We are looking for candidates with 9+ years of industry experience, strong technical expertise, and the ability to collaborate effectively in a global environment.
Responsibilities
- Lead the design and implementation of digital subsystems and protocol-based architectures.
- Define specifications, write and verify RTL using Verilog/SystemVerilog.
- Debug and validate designs across simulation and emulation platforms.
- Collaborate with architecture, verification, and integration teams to deliver production-quality silicon.
- Apply scripting/programming (Python, Perl, TCL, etc.) for automation and workflow improvements.
- Drive project planning, workload management, and effective cross-team collaboration.
Requirements
- Master's degree in EE/CE or related field.
- 10+ years of experience in ASIC/IC design.
- Strong background in digital architecture and protocol design.
- Proficiency in RTL design and verification flows.
- Solid debugging expertise and strong communication skills in English.
- Proven ability to work in agile, international teams.