This position will support our client in advanced chip verification, contributing directly to world-class product development. You will be involved in cutting-edge design verification processes, collaborating with global teams, and playing a key role in ensuring first-silicon success. This is an excellent opportunity to gain exposure to advanced semiconductor technologies and develop expertise in large-scale, international projects.
【Job Responsibilities】
- Collaborate with team members to apply functional verification techniques, improving pre-silicon verification quality and Time to Market.
- Provide technical leadership to the DV team within the project.
- Independently handle DV tasks and guide junior engineers.
- Participate in DV environment setup/porting, block/chip-level test plan creation, coverage analysis, and regression cleanup.
【Basic Qualifications】
- Master's degree in Electrical Engineering, Computer Science, or related field.
- Solid understanding of ASIC design and verification flow.
- Strong RTL coding skills in Verilog/SystemVerilog and familiarity with front-end design flow.
- Proficiency in C/C++ and scripting languages (Perl, Python, etc.).
- Experience with verification methodologies such as UVM, OVM, SVA, or OVL.
【Preferred Qualifications】
- MSEE with 3+ years, or BSEE with 5+ years of experience in digital ASIC/SoC design verification.
- Hands-on experience with DV environment development, automation, and regression infrastructure.
- Familiarity with Linux OS and version control tools (Git, Perforce, or SVN).
- Ability to quickly learn new tools and programming languages, with a passion for improving verification efficiency.
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Working Location
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- Taipei Nangang or Hsinchu