Job Description:
- Implement and maintain simulation environment for IP and SOC level designs
- Familiar with System Verilog (including assertion) and UVM
- Familiar with computer architecture and AMBA protocol, e.g., AXI, AHB_Lite, APB
- Responsibility for test planning, testbench documentation and development
Job Conditions:
Nice-to-Have
- Have experience in high speed interface protocol, e.g., USB, PCIe
- Have experience in third party VIPs (Candence or Synopsys)
- Have experience in Palladium