Job Description
FPGA platform resource and interface evaluation
Evaluation (complexity vs. performance), RTL implementation and verification of ISP (Image Signal Processing) algorithm on FPGA
Evaluation (complexity vs. performance), RTL implementation and verification of image compression algorithm on FPGA
Evaluation (complexity vs. performance), RTL implementation and verification of error correction algorithm for data storage on FPGA
Evaluation (complexity vs. performance), RTL implementation and verification of data encryption algorithm on FPGA
FPGA system integration including sensor control interface, high-speed data transferring interface, display interface, power control, etc.
Job Requirements
Experience in digital design and verification on FPGA platform
Experience in ISP, compression, error correction and encryption algorithm and application is better
Experience in high-speed interface, sensor interface and display interface is better